1. Field of the Invention
The present invention relates to a negative voltage generating circuit, which is provided on a same chip as another semiconductor circuit such as a flash memory to generate and output a negative voltage.
2. Description of the Related Art
A negative voltage is typically used to erase a content stored in a flash memory. However, a voltage supplied to the flash memory is typical a positive voltage, and the negative voltage is not supplied. Thus, a negative voltage generating circuit is provided on the same chip as the flash memory and is used to generate the negative voltage.
FIG. 1 is a block diagram showing the structure of a conventional negative voltage generating circuit. The conventional negative voltage generating circuit will be described with reference to FIG. 1.
This conventional negative voltage generating circuit is composed of a voltage dividing circuit 82, a comparing circuit 3, an oscillator 4, a clock buffer 5, a negative voltage charge pump 6.
The voltage dividing circuit 82 divides a voltage between a negative voltage 104 and a power supply voltage Vcc to output a divided voltage 102. The comparing circuit 3 compares a voltage value of a reference voltage 120 with a voltage value of the divided voltage 102. The comparing circuit 3 sets an oscillator control signal 103 to an active state when the voltage value of the divided voltage 102 is equal to or higher than that of the reference voltage 120, and sets the oscillator control signal 103 to an inactive state when the voltage value of the divided voltage 102 is lower than that of the reference voltage 120.
A specific structure of the comparing circuit 3 will be described with reference to FIG. 2. Referring to FIG. 2, the comparing circuit 3 is composed of a resistor 97, P-channel MOS transistors 91 and 92 of a current mirror circuit, a P-channel MOS transistor 93 whose gate receives the reference voltage 120, a P-channel MOS transistor 94 whose gate receives the divided voltage 102, N-channel MOS transistors 95 and 96 of a current mirror circuit and an inverter 98.
In the P-channel MOS transistor 91, a current determined based on the property thereof and the resistor 97 flows between a source and a drain of the transistor 91. The current having the same current value as that flowing through the transistor 91 flows between a source and a drain of the P-channel MOS transistor 92, which constitutes the current mirror together with the P-channel MOS transistor 91. In this way, the P-channel MOS transistor 92 functions as a current source that supplies the current to the P-channel MOS transistors 93 and 94. The N-channel MOS transistors 95 and 96 constituting the current mirror circuit are respectively connected to the P-channel MOS transistors 93 and 94 as the loads thereto.
When the voltage value of the divided voltage 102 is equal to or higher than that of the reference voltage 120, the current flowing between a source and a drain of the P-channel MOS transistor 94 is decreased. When the divided voltage 102 is lower than the reference voltage 120, the current flowing between the source and the drain of the P-channel MOS transistor 94 is increased. As a result, when the divided voltage 102 is equal to or higher than the reference voltage 120, a voltage outputted to the inverter 98 is decreased. When the divided voltage 102 is lower than the reference voltage 120, the voltage outputted to the inverter 98 is increased. In this way, the voltage supplied to the inverter 98 is changed in a range of a certain amplitude, in accordance with whether the divided voltage 102 is higher or lower than the reference voltage 120. Thus, when a logical threshold of the inverter 98 is set to a value within the amplitude, the oscillator control signal 103 can be generated to indicate whether the divided voltage 102 is higher or lower than the reference voltage 120.
The oscillator 4 generates and outputs two oscillator output signals 105 and 106 whose phases become opposite to each other, when the oscillator control signal 103 is in the active state. A specific structure of the oscillator 4 will be described with reference to FIG. 3.
As shown in FIG. 3, the oscillator 4 is a ring oscillator composed of a NAND circuit 110 and inverters 111.sub.1 to 111.sub.6.
The NAND circuit 110 is provided in a loop of this ring oscillator. The oscillator control signal 103 is supplied to one input terminal of the NAND circuit 110. Thus, the oscillator control signal 103 is used to stop the operation of the oscillator 4, when the oscillator control signal 103 is in the inactive state of a low level. The inverters 111.sub.1 to 111.sub.6 are connected in series in the form of a ring. An output of the inverter 111.sub.6 is outputted as an oscillator output signal 105, and an output of the inverter 111.sub.5 is outputted as an oscillator output signal 106.
FIGS. 4A to 4C are timing charts showing operations of the oscillator control signal 103 and the oscillator output signals 105 and 106. Referring to FIG. 4A to 4C, it could be understood that when the oscillator control signal 103 is in the active state of a high level, Vcc, the two oscillator output signals 105 and 106 whose phases are opposite to each other are outputted, and when the oscillator control signal 103 is in the inactive state of a low level, GND, the oscillator output signals 105 and 106 are not outputted.
As shown in FIG. 5, the clock buffer 5 receives the oscillator output signals 105 and 106 outputted from the oscillator 4, and then outputs as complementary pulse signals 107 and 108 though inverters 121 and 122 and inverters 123 and 124, respectively.
The negative voltage charge pump 6 generates and outputs the negative voltage 104 from the complementary pulse signals 107 and 108. A specific structure of the negative voltage charge pump 6 will be described with reference to FIG. 6.
As shown in FIG. 6, the negative voltage charge pump 6 is composed of P-channel MOS transistors 131.sub.1 to 131.sub.6, capacitors 132.sub.1, to 132.sub.6 and a P-channel MOS transistor 133. The P-channel MOS transistors 131.sub.1, to 131.sub.6 are connected in series such that a gate and a source of each P-channel MOS transistor are connected to each other and further a source of one transistor and a drain of another transistor are connected to each other between the transistors adjacent to each other.
The drains of the P-channel MOS transistors 131.sub.1, 131.sub.3 and 131.sub.5 are connected to the complementary pulse signal 107 through the capacitors 132.sub.1, 132.sub.3 and 132.sub.5, respectively. Also, the drains of the P-channel MOS transistors 131.sub.2, 131.sub.4 and 131.sub.6 are connected to the complementary pulse signal 108 through the capacitors 132.sub.2, 132.sub.4 and 132.sub.6, respectively. The source of the P-channel MOS transistor 131.sub.1 is outputted as the negative voltage 104, and the drain of the P-channel MOS transistor 131.sub.6 is connected to the source of the P-channel MOS transistor 133. The gate and drain of the P-channel MOS transistor 133 are connected to the ground to set the drain of the P-channel MOS transistor 131.sub.6 to a ground potential.
An operation of the negative voltage charge pump 6 will be described below. For the purpose of simple explanation, the operation will be described by using only the P-channel MOS transistor 131.sub.2. However, the operations of the other P-channel MOS transistors 131.sub.1, 131.sub.3 to 131.sub.6 are similar to those of the P-channel MOS transistor 131.sub.2. For the purpose of explanation, the source of the P-channel MOS transistor 131.sub.2 is assumed to be a node 13a, and the drain thereof is assumed to be a node 13b.
At first, it is assumed that at a certain timing, the complementary pulse signal 107 is set to the power supply voltage Vcc and the complementary pulse signal 108 is set to the ground potential. In this case, since the node 13a is raised by the capacitor 132.sub.1, the potential of the node 13a is set to the high level. Also, since the node 13b is lowered by the capacitor 132.sub.2, the potential of the node 13b is set to the low level. When the potential difference between the node 13a and the node 13b is equal to or greater than a threshold, the P-channel MOS transistor 131.sub.2 is in an ON state. At this time, he charges of the node 13a flow into the node 13b whose potential is in the low level. As the charges are decreased at the node 13a, the potential is made lower. Also, as the charges are increased at the node 13b, the potential is made higher. Then, the movement of the charges is continued until the potential of the node 13a becomes equal to that of the node 13b.
At a next timing, the complementary pulse signal 107 is set to the ground potential, and the complementary pulse signal 108 is set to the power supply voltage Vcc. In this case, since the node 13a is decreased to the low level by the capacitor 132.sub.1, the potential of the node 13a is set to the low level. Also, since the node 13b is raised by the capacitor 132.sub.2, the potential of the node 13b is set to the high level. Even if the potential of the node 13b is increased to high level, the gate and the drain maintain the same potential because the gate and the drain are connected to each other. Thus, the P-channel MOS transistor 131.sub.2 remains in the OFF state. However, the above mentioned movement of the charges is performed in the P-channel MOS transistors 131.sub.1 and 131.sub.3 which are adjacent to the P-channel MOS transistor 131.sub.2.
The complementary pulse signals 107 and 108 are alternately switched between the power supply potential level and the ground potential level, and further the P-channel MOS transistors 131.sub.1, to 131.sub.6 repeat the above mentioned operation. Accordingly, the charges are sequentially transferred in the direction from the P-channel MOS transistor 131.sub.1 to the P-channel MOS transistor 131.sub.6. The source of the P-channel MOS transistor 131.sub.1 is set to the lowest potential in the negative voltage charge pump 6, and outputted as the negative voltage 104.
The operation of the conventional negative voltage generating circuit will be described below with reference to FIG. 1.
If the negative voltage 104 is higher than a desired voltage value, the divided voltage 102 is higher than the reference voltage 120. Thus, the comparing circuit 3 sets the oscillator control signal 103 to the active state. The oscillator 4 generates and outputs the oscillator output signals 105 and 106 in response to the active oscillator control signal 103. Then, the clock buffer 5 receives the oscillator output signals 105 and 106, and then outputs the complementary pulse signals 107 and 108. For this reason, the negative voltage charge pump 6 functions to decrease the voltage value of the negative voltage 104.
When the negative voltage 104 reaches the desired voltage so that the divided voltage 102 outputted from the voltage dividing circuit 82 becomes equal to the reference voltage 120, the oscillator 4 does not output the oscillator output signals 105 and 106, because the comparing circuit 3 sets the oscillator control signal 103 to inactive state. The negative voltage charge pump 6 stops the operation in response to the inactive oscillator control signal 103. Also, the voltage value of the negative voltage 104 remains in the defined voltage value.
The thus-generated negative voltage 104 is used to erase the content stored in the flash memory. However, another problem occurs that as the negative voltage 104 is made higher, the erasing time in a memory cell is increased longer. On the other hand, when the negative voltage 104 is made lower, the erasing time becomes shorter. However, another problem occurs of reliability, such as a deterioration of a data retaining property of the memory cell. The optimal voltage value becomes a limited voltage value, in view of these conditions. Hence, the optimal operation for the flash memory requires that the voltage value of the negative voltage 104 has a high accuracy.
In the conventional negative voltage generating circuit, the power supply voltage Vcc and the negative voltage 104 are divided by the voltage dividing circuit 82 to generate the divided voltage 102. However, the voltage value of the power supply voltage Vcc externally applied is different on the basis of the used situation. Hence, the high accuracy can not be attained in the voltage value of the negative voltage 104.
In order to solve the above mentioned, problem, as shown in FIG. 7, it could be considered that a ground potential with a little variation is applied to the voltage dividing circuit 82 instead of the power supply voltage Vcc, a voltage between the ground potential and the negative voltage 104 is divided so as to generate the negative voltage 102. In this case, the negative voltage 104 with the high accuracy could be generated.
However, this negative voltage generating circuit shown in FIG. 7 requires that a negative potential is supplied to the comparing circuit 3 as the reference voltage 120. This results in a complex circuit structure of the comparing circuit 3.
In this way, in the conventional negative voltage generating circuit, there are the following problems:
(1) when the voltage between the power supply voltage and the negative voltage is divided so as to generate the divided voltage, the negative voltage with the high accuracy can not be generated because of the influence of the variation in the power supply voltage; and PA1 (2) when the voltage between the ground and the negative voltage is divided so as to generate the divided voltage, a negative voltage is required as the reference voltage of the comparing circuit, resulting in the complex structure of the comparing circuit. PA1 dividing a difference voltage between a constant internal voltage and a negative voltage to produce a division voltage; PA1 comparing a reference voltage and the division voltage; and PA1 generating the negative voltage based on the comparing result.